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fn6657 rev 3.00 page 1 of 16 october 28, 2014 fn6657 rev 3.00 october 28, 2014 ISL8201M 10a, high efficiency dc/dc module datasheet the ISL8201M is a 20v, 10a out put current, variable output step-down power supply. included in the 15mmx15mm package is a high performance p wm controller switching at 600khz, power mosfets, an inductor, and all the passive components required for complete dc/dc power solution. the ISL8201M operates over an i nput voltage range of 1v to 20v and supports an output voltage range of 0.6v to 5v, which is set by a single divid ing resistor. this high efficienc y power module is capable of del ivering 10a (17a peak) output with up to 95% efficiency, needi ng no heat sinks or airflow to meet power specifications. only bulk input and output capacitors are needed to finish the design. utilizing voltage-mode control, the output voltage can be precisely regulated to as low as 0.6v with up to 1% output voltage regulation. the ISL8201M a lso features internal compensation, internal soft-star t, auto-recover y overcurrent protection, an enable option, and pre-biased output start-up capability. the ISL8201M is packaged in a thermally enhanced, compact (15mmx15mm) and low profile (3.5mm) overmolded qfn package module suitable for automated assembly by standard surface mount equipm ent. the ISL8201M is rohs compliant. typical schematic features ? complete switch m ode power supply ? bias voltage range from +4.5 to +14.4v - wide input voltage range from 1v up to 20v (see input voltage considerations on page 11 ) ? 10a dc output current, 17a peak output current ? adjustable +0.6v to +5v output range ? up to 95% efficiency ? simple voltage mode control ? fixed 600khz switching frequency ? fast transient response ? enable function option ? pre-biased output start-up capability ? internal soft-start ? overcurrent protectio n by low-side mosfet r ds(on) sensing (non-latching, auto-recovery) ? small footprint, low profile surface mount qfn package (15mmx15mmx3.5mm) ? rohs compliant applications ?servers ? industrial equipment ? point of load regulation ? other general pur pose step-down dc/dc ? telecom and datacom applications p gnd f b c omp/en v in v out p hase i sen p vcc (+5v / +12v) v in v out c in c out r fb ISL8201M pgnd vin vout fb pvcc (+4.5v to +20v) v in v out c in c out r fb c pvcc (+5v/+12v) or (+6.5v to 14.4v) p vcc ISL8201M 1.8v 10a 4.87k
ISL8201M fn6657 rev 3.00 page 2 of 16 october 28, 2014 simplified block diagram ordering information part number ( notes 1 , 2 , 3 ) part marking package (rohs compliant) pkg. dwg. # ISL8201Mirz ISL8201M 15 ld qfn l15.15x15 ISL8201Meval1z evaluation board 1. add -t suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil plastic packaged products are rohs compliant b y eu exemption 7c-i and employ special pb-free material sets, m olding compounds/die attach materials, and 100% matte tin plate plus a nneal (e3) termination finish which is compatible with both snp b and pb-free soldering operations. intersil rohs compliant products are msl classified at pb-free peak reflow temperatures that meet or exc eed the pb- free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see product info rmation page for ISL8201M . for more information on msl please see techbrief tb363 . driver driver gate control logic por and soft-start ldo + - pwm controller + - 0.6v 0.4v oscillator dis + - pwm sample and hold + - 21.5a iset inhibit pvcc rfb-ti rset-in pgnd fb comp/en pvcc phase pgnd vout vin iset figure 1. internal block diagram
ISL8201M fn6657 rev 3.00 page 3 of 16 october 28, 2014 pinout ISL8201M (15 ld qfn) top and 3d view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 pin descriptions pin symbol description 1, 2, 3, 4, 11 pgnd power ground. connect to ground plane direc tly. 5 pvcc supply voltage. connect 1f ceramic capacitor to ground plane directly. 6, 8, 15 nc do not connect. 7 iset overcurrent protection. integrated internal 3.57k ? resistor. connect additional resistor between this pin and pgnd pin can change initial setting. 9 vin power input. connect to input. 10 phase phase node. node of high-side and low-side mosfets and output inductor connection. 12 vout power output. connect to output. 13 comp/en compensation and enable. 14 fb feedback input. connect resistor between this pin and gro und for adjusting output voltage.
ISL8201M fn6657 rev 3.00 page 4 of 16 october 28, 2014 absolute maximum ratings thermal information c omp/en to p gnd . . . . . . . . . . . . . . . . . . . . . . . . p gnd - 0.3v to +6v i set to p gnd . . . . . . . . . . . . . . . . . . . . . p gnd - 0.3v to p vcc + 0.3v p vcc to p gnd . . . . . . . . . . . . . . . . . . . . . . . . . . p gnd - 0.3v to +15v p hase to p gnd . . . . . . . . . . . . . . . . . . . . . . . . -1.2v ~ +30v ( note 4 ) v in to p hase . . . . . . . . . . . . . . . . . . . . . . . . . -1.2v ~ +30v ( note 4 ) thermal resistance (typical) ? ja (c/w) ? jc (c/w) 15 ld qfn ( notes 5 , 6 ) . . . . . . . . . . . . 13 2 junction temperature t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125c storage temperature range t stg . . . . . . . . . . . . .-55c to +125c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating ratings input supply voltage (v in ) . . . . . . . . . . . . . . . . . . . . . . +1v to +20v output voltage (v out ) . . . . . . . . . . . . . . . . . . . . . . . . . +0.6v to +5v p vcc fixed supply voltage . . . . . . . . . . . . . . . . . . . . . . . . +5v or +12v wide range supply . . . . . . . . . . . . . . . . . . . . . . + 6.5v to +14.4v ambient temperature range (t a ) . . . . . . . . . . . . . . -40c to +85c caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. v ds (drain-to-source) specification for internal high-side and low -side mosfet. 5. ? ja is measured in free air with the component mounted on a high e ffective thermal conductivity tes t board (i.e. 4-layer type wit hout thermal vias C see tech brief tb379 ) per jedec standards except that the top and bottom layers ass ume solid planes. 6. for ? jc , the case temp location is the center of the exposed metal p ad on the package underside. electrical specifications t a = +25c. v in = 12v, v out = 1.5v. c in = 220fx1, 10f/ceramicx2, c out = 330f (esr = 10m ? ), 22f/ceramicx3. parameter symbol conditions min typ max units input characteristics input supply bias current i q(vin) i out = 0a, v out = 1.5v, v in = 12v, p vcc = 12v - 10 - ma input in-rush current i inrush i out = 0a, v out = 1.5v, v in = 12v, p vcc = 12v - 140 - ma input supply current i s(vin) i out = 10a, v out = 1.5v, v in = 12v, p vcc = 12v - 1.48 - a output characteristics output continuous current range i out(dc) v in = 12v, v out = 1.5v 0 - 10 a line regulation accuracy ? v out / ? v in v out = 1.5v, i out = 0a, v in =3.3v to 20v, p vcc = 12v - 0.1 - % load regulation accuracy ? v out / ? i out i out = 0a to 10a, v out = 1.5v, v in = 12v, p vcc = 12v - 0.5 - % peak-to-peak output ripple voltage ? v out i out = 10a, v out = 1.5v, v in = 12v, p vcc = 12v - 20 - mv dynamic characteristics voltage change for positive load step ? v out-dp i out = 0a to 5a. current slew rate = 2.5a/s, v in = 12v, v out = 1.5v, p vcc = 12v - 36 - mv voltage change for negative load step ? v out-dn i out = 0a to 5a. current slew rate = 2.5a/s, v in = 12v, v out = 1.5v, p vcc = 12v - 39 - mv controller shutdown pvcc supply current i pvcc_s p vcc = 12v; disabled ( note 7 ) 4 5.27 ma supply voltage p vcc fixed 5v supply 4.5 5.0 5.5 v wide range supply 6.5 12.0 14.4 v p vcc operating current i pvcc i out = 10a, v out = 1.5v v in = 12v 5v supply - 22 - ma 12v supply - 47 - ma rising p vcc threshold v porr ( note 7 ) 3.9 4.1 4.3 v p vcc power-on-reset threshold hysteresis v porh ( note 7 ) 0.30 0.35 0.40 v oscillator frequency f osc ( note 7 ) 510 600 660 khz
ISL8201M fn6657 rev 3.00 page 5 of 16 october 28, 2014 internal resistor between v out and fb pins r fb-ti 9.66 9.76 9.85 k ? disabled threshold voltage (comp/en) v endis ( note 7 ) 0.375 0.4 0.425 v reference voltage v ref ( note 7 ) - 0.6 - v reference voltage tolerance 0c to +70c ( note 7 )-1.0- +1.0 % -40c to +85c ( note 7 )-1.5- +1.5 % fault protection internal resistor between i set and p gnd pins r set-in - 3.57- k ? i set current source i set ( note 7 ) 18.0 21.5 23.5 a note: 7. parameters are 100% tested for internal ic prior to module as sembly. electrical specifications t a = +25c. v in = 12v, v out = 1.5v. c in = 220fx1, 10f/ceramicx2, c out = 330f (esr = 10m ? ), 22f/ceramicx3. (continued) parameter symbol conditions min typ max units typical performance characteristics efficiency performance t a = +25c, v in = p vcc (p vcc = 5v for 18v in ), c in = 220fx1, 10f/ceramicx2, c out = 330f (esr = 10m ? ), 22f/ceramicx3. the efficiency equation is: figure 2. efficiency vs load current (5v in ) figure 3. efficiency vs load current (12v in ) figure 4. efficiency vs load current (18v in ) figure 5. 1.2v transient response efficiency output power input power ----------------------------------------- p out p in --------------- - v out xi out ?? v in xi in ?? -------------------------------------- === 30 40 50 60 70 80 90 100 04810 load current (a) efficienc (%) 1.2v 26 0.8v 3.3v 2.5v 1.5v 30 40 50 60 70 80 90 100 010 load current (a) efficienc (%) 2468 0.8v 1.2v 1.5v 2.5v 3.3v 5.0v 30 40 50 60 70 80 90 100 010 load current (a) efficienc (%) 2468 1.2v 1.5v 2.5v 3.3v 5.0v v in = 12v v out = 1.2v i out = 0a to 5a
ISL8201M fn6657 rev 3.00 page 6 of 16 october 28, 2014 transient response performance t a = +25c, v in = 12v, v out = 1.5v, p vcc = 12v, c in = 220fx1, 10f/ceramicx2, c out = 330f (esr = 10m ? ), 22f/ceramicx3 i out = 0-5a (10a), current slew rate = 2.5a/s figure 6. 1.5v transient response figure 7. 1.8v transient response figure 8. 2.5v transient response figure 9. 3.3v transient response typical performance characteristics (continued) v in = 12v v out = 1.5v i out = 0a to 5a v in = 12v v out = 1.8v i out = 0a to 5a v in = 12v v out = 2.5v i out = 0a to 5a v in = 12v v out = 3.3v i out = 0a to 5a pgnd phase vin vout fb comp/en iset pvcc 1.8v 10a v out c out1 22f 6.3v x3 r fb 4.87k c pvcc ISL8201M (+5v/+12v) v in c in (cer) 10f 25v x2 c in (bulk) 220f c out2 330f figure 10. typical application
ISL8201M fn6657 rev 3.00 page 7 of 16 october 28, 2014 pin functions pgnd (pins 1, 2, 3, 4, 11) power ground pin for signal, i nput, and output r eturn path. pgn d needs to connect to one (or more) ground plane(s) immediately, which is recommended to minimize the effect of s witching noise, copper losses, and maximize heat dissipation. pvcc (pin 5) this pin provides the bias supp ly for ISL8201M, as well as the low-side mosfets gate and hi gh-side mosfets gate. if pvcc rises above 6.5v , an internal 5v regul ator will supply to the internal logics bias (but high-side and low-side mosfet gate will still be sour ced by pvcc). connect a well decoupled +5v or +12v supply to this pin. nc (pins 6, 8, 15) these pins have no function; do not connect. iset (pin 7) the iset pin is the input for the overcurrent protection (ocp) setting, which compares the r ds(on) of the low-side mosfet to set the overcurrent threshol d. the ISL8201M has an initial protect overcurrent limit. it has an integrated internal 3.57k ? resistor (r set-in ) between the iset a nd pgnd pins, which can prevent significant overcu rrent impact to the module. one can also connect an additional resistor r set-ex between the iset pin and the pgnd pin in order to reduce the current limit point by paralleling. vin (pin 9) power input pin. apply input vol tage between the vin pin and pgnd pin. it is recommended to place an input decoupling capacitor directly between the vin pin a nd the pgnd pin. the input capacitor should be placed as closely as possible to the module. phase (pin 10) the phase pin is t he switching node bet ween the high and low-side mosfet. it also returns the current path for the high- side mosfet driver and detec ts the low-side mosfet drain voltage for the overcurrent limits point. vout (pin 12) power output pin. apply output load between this pin and the pgnd pin. it is recommended to place a high frequency output decoupling capacitor directly between the vout pin and the pgnd pin. the output capacitor should be placed as closely as possible to the module. comp/en (pin 13) this is the multiplexed pin of the ISL8201M. during soft-start and normal converter operation, this pin r epresents the output of the error amplifier. use co mp/en in combination with the fb pin to compensate for the vo ltage control feedback loop of the converter. pulling comp/en low (v endis = 0.4v nominal) will disable (shut-down) the c ontroller, which causes the oscillator to stop, a nd the high-side gate and low-side gate of the mosfets outputs to be held low. the external pull-down device will initially need to o vercome a maximum of 5ma of comp/en output current. howeve r, once the controller is disabled, the comp/e n output will also be di sabled, thus only a 20a current source will continue to d raw current. fb (pin 14) the fb pin is the output voltage adjustment of the ISL8201M. it will regulate to 0.6v at the fb p in with respect to the pgnd pi n. the ISL8201M has an integrated voltage dividing resistor. this is a precision 9.76k ? resistor (r fb-ti ) between the vout and fb pins. different output v oltages can be programmed with additional resistors between fb to pgnd. reference circuitry for general applications typical application wi th single power supply figure 11 shows the ISL8201M application schematic for input voltage +5v or +12v. the pvcc pin can connect to the input supply directly. typical application with separated power supply figure 12 shows the ISL8201M applicat ion schematic for wide input voltages from +1v to +20v. the p vcc supply can source +5v/+12v or +6.5v to 14.4v. figure 11. typical application schematic pgnd fb comp/en vin vout phase iset pvcc (+5v/+12v) v in v out c in c out r fb r set-ex c pvcc ISL8201M figure 12. wide input voltage application schematic pgnd fb comp/en vin vout phase iset pvcc (+1v to +20v) v in v out c in c out r fb r set-ex c pvcc (+5v/+12v) or (+6.5v to 14.4v) p vcc ISL8201M
ISL8201M fn6657 rev 3.00 page 8 of 16 october 28, 2014 applications information the typical ISL8201M applicati on schematic for input voltage +5v or +12v is shown in figure 11 . external component selection is primarily determine d by the maximum load current and input/output voltage. programming the output voltage the ISL8201M has an internal 0 .6v 1.5% reference voltage. programming the output voltage requires a dividing resistor (r fb ). the output voltage can be calculated as shown in equation 1 : note: ISL8201M has integrated 9.76k ? resistance into the module (dividing resistor fo r top side). the resistance corresponding to different output voltages is as shown in table 1 : initialization (por and ocp sampling) figure 13 shows a start-up wa veform of ISL8201M. the power-on-reset (por) function c ontinually monitors the bias voltage at the pvcc pin. once the rising por threshold has exceeded 4v (v porr nominal), the por function initiates the overcurrent protection (ocp) sample and hold operation (while comp/en is ~1v). when the sampling is complete, v out begins the soft-start ramp. if the comp/en pin is held low during power-up, the initialization will be delayed until the comp/en is released an d its voltage ri ses above the v endis trip point. figures 14 and 15 show a typical power-up sequence in more detail. the initialization starts at t 0 , when either p vcc rises above v porr , or the comp/en pin is released (after por). the comp/en will be pulled up by an internal 20a current source, however, the timing will not begin until the comp/en exceeds the v endis trip point (at t 1 ). the external capacitance of the disabling device, as well as the compensation capacitors, will determine how quickly the 20a current source will charge the comp/e n pin. with typical values, it should add a small delay compared to the soft-start times. the comp/en will continue to ramp to ~1v. from t 1 , there is a nominal 6.8ms delay, which allows the pvcc pin to exceed 6.5v (if rising up towards 12v), so that the internal bias regulato r can turn on cleanly. at the same time, the iset pin is initialized by disabling the lo w-side gate driv er and drawing i set (nominal 21.5a) through r seti . this sets up a voltage that will represent the i set trip point. at t 2 , there is a variable time period for the ocp sample and hold operation (0.0ms to 3.4ms nominal; t he longer time occurs with the higher overcurrent setting). the sample and hold uses a digital counter and dac to save the voltage, so the stored value does not degrade, as long as the p vcc is above v porr (see overcurrent protection (ocp) on page 10 for more details on the equations and variables). u pon the completion of sample and hold at t 3 , the soft-start operatio n is initiated, and the output voltage ramps up between t 4 and t 5 . table 1. resistance to output voltages v out 0.6v 1.05v 1.2v 1.5v r fb open 13k 9.76k 6.49k v out 1.8v 2.5v 3.3v 5v r fb 4.87k 3.09k 2.16k 1.33k v out 0.6 1 9.76k r fb -------------- - + ?? ?? ? = (eq. 1) figure 13. por and soft-start operation pvcc v out comp/en ~4v figure 14. i set and soft-start operation t 0 t 1 comp/en iset vout t 1 t 0 iset v out comp/en
ISL8201M fn6657 rev 3.00 page 9 of 16 october 28, 2014 soft-start and pre-biased outputs the soft-start internally r amps the refer ence on the non-inverting termina l of the error amp fr om 0v to 0.6v in a nominal 6.8ms. the output volt age will thus follow the ramp, from zero to final value, in the same 6.8ms (the actual ramp seen on the v out will be less than the nominal time), due to some initialization timing, between t 3 and t 4 . the ramp is created digitally, so there will be 64 small discre te steps. there is no simple way to change this ramp rate externally. after an initialization period (t 3 to t 4 ), the error amplifier (comp/en pin) is enabled and begi ns to regulate the converter's output voltage during soft-start . the oscillator's triangular waveform is compared to the ramping error amplifier voltage. th is generates phase pulses of incr easing width th at charge the output capacitors. when the inter nally generated soft-start vol tage exceeds the reference voltage (0.6 v), the soft-start is complet e and the output should be in regul ation at the expected voltage. this method provides a rapid and controlled output voltage rise ; there is no large in-rush curr ent charging the output capacitor s. the entire start-up s equence from por typi cally takes up to 17ms; up to 10.2ms for the delay and ocp sample and 6.8ms for the soft-start ramp. figure 16 shows the normal curve for start-up; initialization begins at t 0 , and the output ramps between t 1 and t 2 . if the output is pre-biased to a volta ge less than the expected value (as shown figure 17 ), the ISL8201M will det ect that condition. neither internal mosfet will turn on until the soft-start ramp voltage exceeds the output; v out starts seamlessly ramping from there. if the output is pre-biased to a voltage above the expected val ue (as shown figure 18 ), neither mosfet will turn on until the end of the soft-start, at which time it will pull the output voltag e down to the final value. any resisti ve load connected to the output will help pull down the voltage (at the rc rate of the r of the load and the c of the output capacitance). figure 15. i set and soft-start operation iset t 1 t 2 t 3 t 4 t 5 comp/en iset v out 3.4ms 3.4ms figure 16. normal start-up figure 17. pre-biased start-up t 0 t 1 t 2 v out v out
ISL8201M fn6657 rev 3.00 page 10 of 16 october 28, 2014 if the v in for the synchronous buck converter is from a different supply that co mes up after p vcc , the soft-start will go through its cycle, but with no out put voltage ramp. when v in turns on, the output will follow the ramp of the v in from zero up to the final expecte d voltage (at close to 100% duty cycle, with comp/en pin >4v). if v in is too fast, there may be excessive in-rush current charging the output capacitors (only the beginning of the ramp, from zero to v out matters here). if this is not acceptable, then consider changing the sequencing of the power supplies, sharing the same supply, or adding sequencing logic to the comp/en pin to delay the soft-start until the v in supply is ready (see input voltage considerations on page 11 ). if ISL8201M is disabled after so ft-start (by pulling comp/en pin low), and afterwards enabl ed (by releasing the comp/en pin), then the full initializatio n (including ocp sample) will take place. however, there is no new ocp sampling during overcurrent retries. if the output is shorted to g nd during sof t- start, the ocp will handle it, as described in the next section . overcurrent protection (ocp) the overcurrent function protec ts the converter from a shorted output by using the low-side mosfet on-resistance, r ds(on) , to monitor the current. a resistor (r set ) programs the overcurrent trip level. this method enhances the conver ter's efficiency and reduces cost by eliminating a current sensing resist or. if overcurrent is detected, the output immediately shuts off. it cycles the soft- start function in a hiccup mode (2 dummy soft-start time-outs, then up to one real one) to provi de fault protection. if the shorted condition is not removed, this cycle will continue indefinitely. following por (and 6.8ms delay ), the ISL8201M initiates the overcurrent protection sample and hold operation. the low- side gate driver is disabled to allow an internal 21.5a curren t source to develop a voltage across r set . the ISL8201M samples this voltage (which is r eferenced to the pgnd pin) at the iset pin, and hold s it in a counter and dac combination. this sampled voltage is held inte rnally as the overcurrent set point, for as long as power is a pplied, or until a new sample i s taken after coming out of a shut-down. the actual monitoring of the low-side mosfet on-resistance starts 200ns (nominal) after the edge of the internal pwm logic signal (that creates the rising external low-side gate signal). this is done to allow the gate t ransition noise and ringing on the phase pin to settl e out before monitori ng. the monitoring ends when the internal pwm edge (and thus low-side gate signal) goes low. the ocp can be detected anywhere within the above window. if the converter is r unning at h igh duty cycles around 75% for 600khz operation, then the low-side gate p ulse width may not be wide enough for the ocp t o properly sample the r ds(on) . for those cases, if the low-side gate signal is too narrow (or not there at all) for 3 consecu tive pulses, then the third puls e will be stretched and/or inserte d to the 425ns minimum width. this allows for ocp monitoring every third pulse under this condition. this can introduce a small pulse-width error on the output voltage, which will be corrected on the next pulse; and the output ripple voltage will have an unusual 3-clock pattern, which may look like jitter. the overcurrent function will tr ip at a peak inductor current (i peak ) determined by equation 2 : where: i set is the internal i set current source (21.5a typical). r set is equivalent resistance be tween iset and pgnd pins. r ds(on) is typically 6.1m ? at (v pvcc = v gs = 10v, i ds = 30a) and 9m ? at (v pvcc = v gs = 4.5v, i ds = 30a). note: ISL8201M has integrated 3.57k ? resistance (r set-in ). therefore, the equivalent resistance of r set can be expressed in equation 3 : the scale factor of 2 doubles t he trip point of the mosfet voltage drop, compared to the setting on the r set resistor. the oc trip point varies in a syst em mainly due to the mosfet r ds(on) variations (i.e. over process, current and temperature). to avoid overcurrent tripping in the normal operating load range, find the r set resistor from equation 4 , and with steps 1 to 3: 1. the maximum r ds(on) at the highest junction temperature 2. the minimum i set from the electrical specifications table on page 3 . figure 18. pre-biased start-up - overcharged v out 500mv/div i peak 2i set r set ? ? r ds on ?? ------------------------------------------- - = (eq. 2) r set r set-ex r set-in ? r set-ex r set-in + ------------------------------------------------------- = (eq. 3)
ISL8201M fn6657 rev 3.00 page 11 of 16 october 28, 2014 3. determine i peak for: where ? i l is the output inductor ripple current. in a high input voltage, high output voltage appl ication, such as 20v input to 5v output, the inductor ripple becomes excessive due to the fixed internal inductor value. i n such applications, the output current will be limited from the rating to approximately 70% of the modules ra ted current. the relationships bet ween the external r set values and the typical output current i out(max) ocp levels are as follows: the range of allowable voltages detected (2 x i set x r set ) is 0mv to 475mv. if the voltage drop across r set is set too low, then this can cause almost contin uous ocp tripping and retry. it will also be very sensitive t o system noise and in-rush curr ent spikes, so it should be avoided. the maximum usable setting is around 0.2v across r set (0.4v across the mosfet); values above this might disable the protection. any voltage drop across r set that is greater than 0.3v (0.6v mosfet trip point) will disable th e ocp. note that cond itions during power- up or during a retry may look different than normal operation. during power-up in a 12v system, the ISL8201M starts operation just above 4v; if the supply ramp is slow, the soft- start ramp might be over wel l before 12v is reached. therefore, with lo w-side gate drive voltages, the r ds(on) of the mosfet will be higher during po wer-up, effectively lowering the ocp trip. in addition, the ripple current will likely be different at a lower input volta ge. another factor is the digit al nature of the soft-start ramp. o n each discrete voltage step, there is in effect, a small load transient and a current spike to charge the output capacitors. t he height of the current spike i s not controlled, however, it is af fected by the step size of the output and the value of the output capacitor s, as well as the internal error amp compensation. therefore, it is possible to trip the overcurrent with in-ru sh current, in addition to the normal load and ripple considerations. figure 19 shows the output respons e during a re try of an output shorted to pgnd. at time t 0 , the output has been turned off due to sensing an overcurrent condition. there are two internal soft-start delay cycles (t 1 and t 2 ) to allow the mosfets to cool down in order to keep the average power dissipation in retry at an acceptable level. at time t 2 , the output starts a normal soft-start cycle, and the output tries to ramp. if the s hort is still applied and the current reaches the i set trip point any time during the soft-start ramp period, the output will shut of f and return to time t 0 for another delay cycle. the retry period is thus two dummy soft-start cycles plus one variab le one (which depends on how long it takes to trip the sensor each time). figure 19 shows an example where t he output gets about half- way up before shutting down; ther efore, the retry (or hiccup) time will be around 17ms. the minimum should be nominally 13.6ms and the maxim um 20.4ms. if the short condition is finally removed, the output should ramp up normally on the next t 2 cycle. starting up into a shorted load lo oks the same as a retry into that same shorted load. in bot h cases, ocp is always enabled during soft-start; once it trips, it will go into retry (hiccup ) mode. the retry cycle will always have two dummy time-outs, plus whatever fraction of the real so ft-start time passes before the detection and shutoff. at that point, the logic immediately sta rts a new two dummy cycle time-out. input voltage considerations figure 12 shows a standard configuration where p vcc is either 5v (10%) or 12v (20%). in eac h case, the gat e drivers use the p vcc voltage for low-side gate and high-side gate driver. in addition, p vcc is allowed to work anywhere from 6.5v up to the 14.4v maximum. the p vcc range between 5.5v and 6.5v is not allowed for long-term reliabi lity reasons, but transitions through it to voltages ab ove 6.5v are acceptable. there is an internal 5v regu lator for bias , which turns on between 5.5v and 6.5v. some of the delay after por is there to allow a typical power supply to ramp-up past 6.5v before the soft-start ramps begins. this prevents a disturbance on the output, due to the internal reg ulator turning on or off. if the transition is slow (not a ste p change), the disturbance should be minimal. thus, while the recommendation is to not have the output enabled during the transit ion through this region, it ma y be acceptable. the user should m onitor the output for their table 2. r set ( ? ) ocp (a) at v in = 12v, p vcc = 5v ocp (a) at v in = 12v p vcc = 12v open 13.3 17.3 50k 12.6 16.6 20k 11.4 14.9 10k 10.2 13.3 5k 7.6 10.3 3k 6.3 8.3 2k 4.9 6.7 i peak i out max ?? ? i l ?? 2 ------------- + ? (eq. 4) figure 19. overcurrent retry operation t 2 t 1 t 0 v out
ISL8201M fn6657 rev 3.00 page 12 of 16 october 28, 2014 application to see if there is any problem. if p vcc powers up first and the v in is not present by the time the initialization is done, then the soft-start w ill not be able to ramp the output, and th e output will later follow part of the v in ramp when it is applied. if this is not desired, then change the sequencing of the supplies , or use the comp/en pin to disable v out until both supplies are ready. figure 20 shows a simple sequencer for this situation. if p vcc powers up first, q 1 will be off, and r 3 pulling to p vcc will turn q 2 on, keeping the ISL8201M in shut-down. when v in turns on, the resistor divider r 1 and r 2 determines when q 1 turns on, which will turn off q 2 and release the shut-down. if v in powers up first, q 1 will be on, turning q 2 off; so the ISL8201M will start-up as soon as p vcc comes up. the v endis trip point is 0.4v nominal, so a wide va riety of n-mosf et or npn bjt or even some logic ic's can be used as q 1 or q 2 . however, q 2 must be low leakage when off (open-drain or open-collector) so as not to inte rfere with the comp output. q 2 should also be placed near the comp/en pin. the v in range can be as l ow as ~1v (for v out as low as the 0.6v reference) and as hi gh as 20v. there are some restrictions for running high v in voltage. the maximum phase voltage is 30v. the vin + p vcc + any ringing or other transients on the phase pin must be less t han 30v. if v in is 20v, it is recommended to limit p vcc to 5v. switching frequency the switching frequency is a fi xed 600khz clock, which is determined by the internal osc illator. however, all of the othe r timing mentioned (por delay, ocp sample, soft-start, etc.) is independent of the clock frequency (unless otherwise noted). selection of the input capacitor the input filter cap acitor should be base d on how much ripple the supply can tolerate on the dc input line. the larger the capacitor, the less ripple expected but consideration should be taken for the higher surge current during power-up. the ISL8201M provides the soft-sta rt function that controls and limits the current surge. the value of the input capacitor can be calculated by equation 5 : where: c in is the input capacitance (f) i in is the input current (a) ? t is the turn on time of the high-side switch (s) ? v is the allowable peak-to-peak voltage (v) in addition to the bulk capacitance, some low equivalent series inductance (esl) ceramic ca pacitance is recommended to decouple between the drain terminal of the high-side mosfet and the source terminal of the low-side mosfet. this is used to reduce the voltage ringing cre ated by the switching current across parasitic circuit elements. output capacitors the ISL8201M is desi gned for low output voltage ripple. the output voltage ripple and transient requirements can be met with bulk output capacitors (c out ) with low enough equivalent series resistance (esr). c out can be a low esr tantalum capacitor, a low esr polymer capacitor or a ceramic capacitor. the typical capacitance is 330f and decoupled ceramic output capacitors are used. the internally optimized loop compensation provides sufficient stability margins for all ceramic capacitor applications with a recommended total value of 400f. additional output filter ing may be needed if further reduction of output r ipple or dynamic transient spike is required. layout guide to achieve stable operation, l ow losses, and good thermal performance some layout considerations are necessary. ? the ground connection between pin 11 and pins 1 to 4 should be a solid ground plane under the module. ? place a high freque ncy ceramic capacito r between (1) vin and pgnd (pin 11) and (2) pvcc and pgnd (pins 1 to 4) as figure 20. sequence circuit v in pvcc r 1 r 2 r 3 q 1 q 2 to comp/en c in i in ? t ? ? v ------------------- = (eq. 5) figure 21. recommended layout v out r fb pgnd c pvcc v in pgnd c in c out1 (decouple)
fn6657 rev 3.00 page 13 of 16 october 28, 2014 ISL8201M intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2009-2014. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. close to the module as possible to minimize high frequency noise. ? use large copper areas for power path (vin, pgnd, vout) to minimize conducti on loss and thermal s tress. also, use multiple vias to connect the powe r planes in different layers. ? keep the trace connection to t he feedback resistor short. ? avoid routing any sensitiv e signal traces near the phase node. thermal considerations experimental power los s curves along with ? ja from thermal modeling analysis can be used to evaluate the thermal consideration for t he module. the derating curves are derived from the maximum power allow ed while maintaining the temperature below the maximu m junction temperature of +125c. in actual application, o ther heat sour ces and design margin should be considered. figure 22. power loss vs load current (5v in ) figure 23. derating curve (5v in ) figure 24. power loss vs load current (12v in ) figure 25. derating curve (12v in ) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 6810 load current (a) loss (w) 0.6v 1.5v 3.3v 2 4 0 2 4 6 8 10 12 60 70 80 90 100 110 ambient temperature (c) max. load current (a) 3.3v 1.5v 0.6v 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 46810 load current (a) loss (w) 02 4.0 0.6v 1.5v 2.5v 3.3v 5.0v 0 2 4 6 8 10 12 60 70 80 90 100 110 ambient temperature (c) max. load current (a) 5.0v 2.5v 3.3v 0.6v 1.5v
ISL8201M fn6657 rev 3.00 page 14 of 16 october 28, 2014 package description the structure of ISL8201M belongs to the quad flat-pack no-lead package (qfn). this kind of package has advantages, such as good thermal and electrical conductivity, low weight an d small size. the qfn package is applicable for surface mounting technology and is being more read ily used in the industry. the ISL8201M contains several types o f devices, including resistors , capacitors, inductors and control ics. the ISL8201M is a copper leadframe based package with e xposed copper thermal pads, which have good electrical and thermal conductivity. the copper leadframe and multi component a ssembly is overmolded with polymer mold compound to protect these devices. the package outline and typical pcb layout pattern design and typical stencil patter n design are shown in the package outline drawing l15.15x15 on page 15 . the module has a small size of 15mmx15mm x 3.5mm. figure 26 shows typical reflow profile parameters. these guidelin es are general design rules. users could modify parameters according to their application. pcb layout pattern design the bottom of ISL8201M is leadf rame footprint, which is attached to pcb by surface mounting process. the pcb layout pattern is shown in the package outline drawing l15.15x15 on page 15 . the pcb layout pattern i s essentially 1:1 with the qfn exposed pad and i/o terminat ion dimensions, except for the pcb lands being a slightly extended distance of 0.2mm (0.4mm max) longer than the qf n terminations, which allows for solder filleting around the periphery of the package. this ensures a more complete and inspectable solder joint. the thermal lands on the pcb lay out should matc h 1:1 with the package exposed die pads. thermal vias a grid of 1.0mm to 1.2mm pitc h thermal vias, which drops down and connects to buried copper plane(s), should be placed under the thermal land . the vias should be about 0.3mm to 0.33mm in d iameter with the barre l plated to about 1.0 ounce copper. although addin g more vias (by decreasing via pitch) will improve the the rmal performance, diminishing returns will be seen as more a nd more vias are added. simply use as many vias as practical f or the thermal land size and your board design rules allow. stencil pattern design reflowed solder joints on the perimeter i/o lands should have about a 50m to 75m (2mil to 3mil) standoff height. the solder paste stencil design is the first step in developing optimized, reliable solder joins. stencil aperture size to land size ratio should typically be 1:1. the aperture wi dth may be reduced slightly to help prevent solder bridging between adjacent i/o lands. to reduce solder paste volume on the larger thermal lands, it is recommended that an array of sma ller apertures be used instead of one large aperture. it is recommended th at the stencil print ing area cover 50% to 80% of the pcb layout pattern. a typical sold er stencil pattern is shown in t he package outline drawing l15.15x15 on page 15 . the gap width betw een pad to pad is 0.6mm. the user should consider the symmetry of the whole stencil pattern when designing its pads. a laser cut, stainless steel stencil with electropol ished trapezoidal wa lls is recommended. electropolishing "smoot hes" the aperture walls resulting in reduced surface fricti on and better paste release which reduces voids. using a trape zoidal section aperture (tsa) also promotes paste release and forms a "brick like" paste deposit that assis ts in firm component placement. a 0.1mm to 0.15mm stencil thickness is recommended for this large pitch (1.3mm) qfn. reflow parameters due to the low mount height o f the qfn, "no clean" type 3 solder paste per ansi/j-std- 005 is recommended. nitrogen purge is also reco mmended during reflow . a system board reflow profile depends on the thermal mass of the entire populated board, so it is not practical to define a specific soldering profile just for the qfn. the profile given in figure 26 is provided as a guideline, t o be customized for varying manufacturing practi ces and applications. figure 26. typical reflow profile 0300 100 150 200 250 350 0 50 100 150 200 250 300 temperature (c) duration (s) slow ramp (3c/s max) and soak from +100c to +180c for 90s~120s ramp rate ? 1.5c from +70c to +90c peak temperature +230c~+245c; typically 60s-7 0s above +220c keep less than 30s within 5c of peak temp.
fn6657 rev 3.00 page 15 of 16 october 28, 2014 ISL8201M package outline drawing l15.15x15 15 lead quad flat no-lead plastic package (punch qfn) rev 3, 8/10 bottom view side view top view 0.2 s 0.05 s s 5 10 9 8 7 6 3 4 2 5 ab s m 0.05 11 10 11 9 7 8 6 ab 0.2 s x4 12 4 3 2 14 13 1 15 7x 1.70 1.125 23x 1.30 0.5 5 all around 15.00.2 13 pin 1 index area 1514 1 12 (33x0.4) 15.00.2 2.10 33x 0.5 5.80 4x 7.90 21x 1.0 4.60 2.20 3.0 4.80 2x 13.80 9.0 5.0 45 3.10 5.90 3.80 1.30 2x 7.70 3.50.2 0.90 1.90 2.90 0.30 2.10 1.80 4x 1.90 6.90 5.10 11x 0.80 6.0000 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05; the configuration of the pin #1 identifier is optional, but mus t be 3. either a mold or mark feature. 2. dimensions are in millimeters. 1. notes: body tolerance 0.1mm 15.80.2 15.80.2
fn6657 rev 3.00 page 16 of 16 october 28, 2014 ISL8201M 6.18 0.00 4.12 3.48 2.82 2.18 1.52 0.88 0.22 0.42 2.38 3.02 3.68 4.32 4.98 5.62 6.28 6.92 8.30 4.90 2.80 1.60 1.00 1.35 2.18 4.30 5.90 6.60 0.00 stencil pattern with square pads-2 0.88 0.0 3.00 3.50 8.30 typical recommended land pattern 8.30 1.70 2.20 4.00 3.00 0.90 0.90 0.0 2.20 0.40 0.40 1.70 2.20 0.0 1.20 5.20 3.10 5.60 4.60 8.30 8.30 package boundary 4.80 6.10 5.60 4.30 4.30 6.70 4.90 stencil pattern with square pads-1 2.50 0.90 0.00 1.40 2.00 4.30 8.30 3.02 4.63 5.27 7.00 3.50 4.15 0.42 2.38 0.22 0.00 1.80 2.20 3.70 4.30 6.60 0.00 0.60 1.20 6.60 3.40 4.80 0.32 0.30 1.63 4.88 5.53 2.93 2.28 0.98 0.33 0.00 6.60 4.20 3.75 0.30 3.15 3.60 0.00 6.08 0.97 1.62 5.52 4.87 4.22 3.57 2.92 2.27 3.75 3.15 6.60 5.53 2.82 2.18 1.52 4.12 3.48 6.07 6.72 7.00 8.30 8.31 7.01 0.32 2.28 3.58 4.88 4.23 2.93 0.32 1.63 0.98 0.00 3.58 2.28 1.62 0.98 2.92 6.99 4.22 5.52 8.29 8.29 8.30 6.00 7.00 5.70 6.20 4.40 4.90 3.10 3.60 1.30 2.30 5.60 4.60 8.30 2.10 8.30 0.90 1.90 3.10 5.10

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